1. Field of the Invention
The present invention relates to a fabricating method of a multi-level wiring structure for a semiconductor device, and more particularly to a fabricating method of a multi-level wiring structure for a semiconductor device using a dual damascene process.
2. Description of the Conventional Art
As the integration of a semiconductor device has increased, it became generalized to apply a multi-level wiring structure which has at least three levels of wiring. In a conventional art, such multi-level wiring structure is fabricated by repeatedly carrying out steps of forming a lower conductive layer pattern on a semiconductor substrate, forming an insulating layer on the lower conductive layer pattern to thereby electrically insulate the lower conductive layer pattern from an upper conductive layer pattern, selectively etching the insulating layer to thereby form a via hole for connecting the lower conductive layer pattern with the upper conductive layer pattern, and forming patterning a conductive layer on the via hole and the insulating layer pattern to thereby form the upper conductive layer pattern. However, according to the fabricating method of the conventional multi-level wiring structure, it is relatively simple to fabricate a simple multi-level wiring structure such as a single or double-level wiring structure. However, when it comes to at least three-level wiring structure, as the wiring level increases, components formed on the semiconductor substrate have severe step difference, which results in short between the lower and upper conductive layer patterns and break of the conductive patterns.
In order to solve the above problems, there has been introduced a damascene process as a fabricating method of a multi-level wiring structure. More specifically, in the damascene process, an insulating film is formed on a lower conductive layer pattern, a trench and a via hole are previously provided, the trench corresponding to an upper conductive layer pattern by etching the insulating film and the via hole being formed at a location corresponding to an interconnect which connects a lower conductive layer with an upper conductive layer, and a conductive film is filled in the trench and the via hole. Since such process has a flat top surface formed after forming the upper conductive layer pattern, the reliability of a semiconductor device is improved because no short or break between conductive wires occurs although the multi-level wiring process is performed.
The fabricating method for the multi-level wiring structure according to the conventional damascene process is disclosed in U.S. Pat. No. 4,789,648. FIGS. 1A through 1E sequentially illustrate an example of the fabricating method for the multi-level wiring structure using the conventional damascene process.
As shown therein, as can be seen in FIG. 1A, a lower conductive layer pattern 12 is formed on a portion of a semiconductor substrate 11, and a first oxide film 13 which is an insulating film is formed on the lower conductive layer pattern 12 and the semiconductor substrate 11. Next, a nitride film is formed as an etching stop film 14 on the first oxide film 13 and a second oxide film 15 is formed on the etching stop film 14 as the insulating film, the etching stop film 14 being formed at a thickness of about 1500 .ANG. and the second oxide film being formed at a thickness of about 5000 .ANG..
Next, as shown in FIG. 1B, the second oxide film 15 and the etching stop film 14 are partially etched to form a trench 16 having a shape corresponding to an upper conductive layer pattern. Here, a depth of the trench 16 is about 6500 .ANG. (that is, the thickness of the etching stop film plus the second oxide film).
Then, a photoresist film is formed on a resultant upper surface of FIG. 1B. Here, a thickness of the photoresist pattern on the second oxide film 15 is to be about 8000-10000 .ANG. because if the thickness of the photoresist film on the second oxide film 15 is formed below 8000 .ANG., during the etching process for forming the via hole the photoresist film is etched and at this time the second oxide film 15 formed right below the photoresist film might be undesirably etched. Accordingly, to prevent the second oxide film 15 from being etched, the thickness of the photoresist film should be thickly provided on the second oxide film 15. To form the photoresist film pattern on the second oxide film 15 at the thickness between 8000-10000 .ANG., a photoresist having 8 centi-poise (cP) of viscosity is formed by a rotary coating at 2000-3000 rpm. While, since the photoresist film of the very low viscosity is formed by the rotary coating, the surface level of the photoresist film formed on the oxide film is almost same as that of the photoresist film formed in the trench. Therefore, the thickness of the photoresist film formed in the trench 16 becomes about 14500-16500 .ANG., that is the depth of the trench plus the thickness of the photoresist film formed on the oxide film.
To form the via hole, as shown in FIG. 1C, a window 18 is formed by performing the photolithography process on a predetermined portion of the photoresist film formed at the trench. The photoresist film becomes a photoresist film pattern 17 with the window 18. Next, the first oxide film 13 is etched by using the photoresist pattern as a mask through the window 18, and then the photoresist film pattern 17 is removed for thereby removing a via hole 19 as can be seen in FIG. 1D. Lastly, a conductive layer (not shown) is formed on the entire surface of the structure of FIG. 1D to fill the via hole 19 and the trench 16, and a chemical mechanical polishing process is performed to form an upper conductive layer pattern 20 as well as an interconnect 21 for connecting the lower and upper conductive layer patterns 12, 20.
However, in the fabricating method for the conventional multi-level wiring structure, there is a problem of performing the photoresist patterning to form the via hole under the condition in which the thickness of the photoresist film formed at the trench. However, in the general photolithography process, as the photoresist film becomes thick, the resolution decreases. That is, as shown in FIG. 5, when the thickness of the photoresist film is, for example, 6900 .ANG., the delineated width is 0.18 .mu.m, while when the photoresist films have the thickness of 10400 .ANG. and 11800 .ANG., the delineated widths are 0.22 .mu. and 0.26 .mu., respectively. That is, if the photoresist film is thickly formed, it is difficult to form a fine pattern. Recently, since the fabrication of at least 256 M DRAM is aimed for achieving a design rule under 0.18 .mu.m, it seems that the design rule can not be achieved because it is impossible to thinly form the photoresist film by using the conventional process.
Further, a depth of focus is ranged between 0.4 to 0.6 .mu.m in the currently developed photolithography process. However, because the photoresist film is formed at the thickness over 14000 .ANG. in the conventional art, although the maximum depth of focus is applied, the photoresist film is thickly formed at the thickness at least twice the maximum depth of focus, that is over 12000 .ANG.. Therefore, the thickness of the photoresist film is out of the allowable range of the depth of focus which leads to bad resolution of the photoresist film. Particularly, when the size of the via hole is very small under about 0.3 .mu.m, bridge occurs between the photoresist film patterns and thus the via hole may not be formed. In addition, in the conventional art, when forming a via hole mask on a predetermined portion of the trench for forming the via hole, the mask has an opening portion which corresponds to the size of the via hole. Therefore, if the position arrange is not properly determined, the actual size of the via hole is formed smaller than the designed size thereof which results in increase in contact resistance between the upper and lower conductive lines or inferior contact therebetween.